Engine

pub const Tier = enum

Execution tier the engine will dispatch through.

`t1_pm4` and `t2_umq` are the two direct AMDGPU paths; `t_cpu` is the reference scalar fallback; `t_metal`, `t_intel`, and `t_cuda` are reserved for the corresponding native backends.

pub const Options = struct

Caller-supplied configuration for `Engine.init`.

Currently just the desired tier; future fields (worker counts, ring depths, telemetry hooks) live here.

pub const Engine = struct

Top-level runtime handle.

Owns the allocator the engine was built with and the selected tier; future revisions will also own the ring backend.

pub fn init(allocator: std.mem.Allocator, options: Options) !Engine

pub fn deinit(self: *Engine) void

pub fn parseTier(value: []const u8) !Tier

Parse a textual tier identifier (e.g.

from `ZINC_RT_TIER` or a CLI flag) into a `Tier`. Accepts both short (`t1`, `t2`) and canonical (`t1_pm4`, `t2_umq`) names; `auto` defers to `autoTier`. not a recognised name.

pub fn tierFromEnv() !Tier

Read `ZINC_RT_TIER` and parse it, falling back to `autoTier` when unset.

pub fn autoTier() Tier

Probe the host for direct-execution paths and return the best available tier.

Tries T2 UMQ first (the blessed AMDGPU user-queue path), falls back to T1 PM4 over `/dev/kfd` when UMQ admission is refused, and finally to the scalar CPU reference. so T2 admission usually fails and we end up on T1 PM4.